1. Field of the Invention
The invention relates to a method of fabricating a memory device, and more particularly, to a method of fabricating a flash memory device.
2. Description of the Related Art
Electrically erasable and programmable read only memory (EEPROM) is currently one the most widely used memory devices applied in personal computers and electronic equipment. A memory cell in a early developed conventional EEPROM comprises a transistor with a floating gate to achieve the operations of writing, erasing, and storing data while electrical shut down. This conventional memory cell typically occupies a large surface area. The data access speed is between 150 ns to 200 ns. A lately developed memory cell has a faster data access speed ranged between 70 ns to 80 ns. This memory cell is named as a flash memory by Intel Co.
In a transistor of a conventional flash memory, the hot electron effect is applied for data storing, and the Fowler-Nordheim tunneling effect is applied for data erasure. While storing data a high voltage of 8V is applied between the drain region and the source region. The controlling gate is biased with the same high voltage at the same time. The hot electrons may thus flow out of the source region. While approaching the drain region, these hot electrons tunnel through the oxide layer and are trapped in the floating gate. This is the so-called drain side injection operation. The threshold voltage of the floating gate is enhanced, and the object of storing data is achieved. By applying a positive voltage to the source region and a negative voltage to the controlling gate, the electrons trapped in the floating gate flow out of the floating gate and tunnel through the oxide layer, and thus, the stored data are erased. The floating gate is retrieved to the status before data storing.
FIG. 1 shows a layout of a conventional flash memory. FIG. 2, 3, 4 are cross sectional views taken along a cutting line I--I in FIG. 1, and FIGS. 5 and 6 are cross sectional views taken along the cutting line II--II in FIG. 1. The cross sectional views of FIG. 3 to FIG. 6 show a conventional process for fabricating a flash memory.
Referring to both FIG. 2 and FIG. 5, a substrate 10 is provided. A pad oxide layer (not shown) is formed on the substrate 10. Using local oxidation, a field oxide layer 14 is formed to define an active region of the substrate 10. Using wet etching, the pad oxide layer is removed. Using thermal oxidation, a tunnel oxide layer 12 with a thickness of 100 .ANG. is formed on the substrate 10. A polysilicon layer having a thickness of 1500 .ANG. is formed on the tunnel oxide layer 12. Using photolithography and etching process, the polysilicon layer is patterned and then denoted by a reference numeral 16 in the figures.
An inter-poly dielectric layer with a thickness of 250 .ANG. is formed to cover the polysilicon layer 16. Another polysilicon layer with a thickness of 3000 .ANG. is formed. Using photolithography and etching process, the polysilicon layer is patterned and denoted by a reference numeral 20 as shown in the figure. Using the polysilicon layer 20 as a mask, a etching process is performed on the polysilicon layer 16 until the substrate 10 is exposed. Thus, a gate of a flash memory is formed by the polysilicon layer 20, the inter-poly dielectric layer 18, the polysilicon layer 16, and the tunnel oxide layer 12.
A photo-resist layer 21 is formed to cover a part of the substrate 10, while the exposed part of the substrate 10 includes the substrate 10 at a side of the gate. By performing heavy phosphorus ion implantation with a tile angle, the exposed substrate 10 is doped. An annealing process is performed to form a tunnel diffusion region 24. The tunnel diffusion region 24 extends toward a region under the gate.
In FIG. 3, the photo-resist layer 21 is removed. Using the polysilicon layer 21 as a mask a heavy arsenic ion implantation is performed on the substrate 10 to form a source region 22a and a drain region 22b. The source region 22a is encompassed by the tunnel diffusion region 24.
Referring to both FIG. 4 and FIG. 6, a dielectric layer 30 is formed to cover the substrate 10. Using photolithography and etching, a contact window 32 is formed to penetrate through the dielectric layer 30 and to expose the drain region 22b. A metal layer 34 is formed to fill the contact window 32, so as to couple with the drain region 22b. The metal layer 34 is used as a bit line.
In the above conventional flash memory, the programming step is operated by hot electrons injected from aside of the drain region. Therefore, a high voltage (8V) is require to provide a high current. An over-erase effect thus often occurs.
In addition, the dimension of the flash memory is restricted by the size of the contact window 32. This flash memory can thus only be shrunk to a certain extend in size. With the formation of the field oxide, the shrinkage is further limited. The low level of planarization is also another drawback for using the field oxide layer. Moreover, the contact window is filled with a metal layer as a bit line, the interference by the reflection from the metal layer is inevitable.